Product Summary
The MC68824FN12H functions as an intelligent peripheral device to a microprocessor. An on chip DMA transfers data frames to and from a buffer memory with minimal microprocessor interference required. A microcoded fully linked buffer management scheme queues frames during transmission and reception, and optimizes memory use. Since the MC68824FN12H bus interface is configurable, the MC68824FN12H can handle both 8bit and 16bit data transfers.
Features
MC68824FN12H features: (1)system clock rate up to 16.67MHz; (2)serial data rates from 10 Kbits/S to 12.5 Mbits/s; (3)IEEE 802.4 recommended serial interface supporting various physical layers; (4)Highly integrated M68000 family bus master interface; (5)simplified interface to other processor environments; (6)Low power consumption through 1.5 micron HCMOS fabrication.
Diagrams
MC6800 |
Other |
Data Sheet |
Negotiable |
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MC6801 |
Other |
Data Sheet |
Negotiable |
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MC68020 |
Other |
Data Sheet |
Negotiable |
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MC68020CEH16E |
Freescale Semiconductor |
Microprocessors (MPU) 32-BIT MPU |
Data Sheet |
Negotiable |
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MC68020CEH25E |
Freescale Semiconductor |
Microprocessors (MPU) 32-BIT MPU |
Data Sheet |
Negotiable |
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MC68020CRC16E |
Freescale Semiconductor |
Microprocessors (MPU) 32-BIT MPU |
Data Sheet |
Negotiable |
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